AT6000 FPGAs - AT6000 FPGAs - Application Note

Edge detection is of fundamental importance in image analysis. Edges character ize object boundar ies , and are thereby very useful for registration, segmentation, and identification of objects in images. For example, an edge detector is commonly found in such applications as contour mapping and target recognition. Similar to some digital signal processing algorithms, edge detection involves two-dimensional convolution, a compute-intensive multiply-add operation. Numerous solutions such as powers-of-2s [1] and vector multipliers have been proposed to alternatively manipulate the multiply-add operation. In this paper, we wil l present a reference design of a fully pipelined bit-parallel edge detection circuit that, with a careful choice of convolver masks, utilizes only pipelined adders and fits into one Atmel AT6010 FPGA. We will also discuss how CacheLogic® optimizes performance of an edge detector operating on real-time video at run-time.